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LTC4300-1/LTC4300-2 Hot Swappable 2-Wire Bus Buffers
FEATURES
s s
DESCRIPTIO
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Bidirectional Buffer for SDA and SCL Lines Increases Fanout Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane Isolates Input SDA and SCL Lines from Output Compatible with I2CTM, I2C Fast Mode and SMBus Standards (Up to 400kHz Operation) Small MSOP 8-Pin Package Low ICC Chip Disable: <1A (LTC4300-1) READY Open Drain Output (LTC4300-1) 1V Precharge on all SDA and SCL Lines Supports Clock Stretching, Arbitration and Synchronization 5V to 3.3V Level Translation (LTC4300-2) High Impedance SDA, SCL Pins for VCC = 0V
The LTC(R)4300 series hot swappable 2-wire bus buffers allow I/O card insertion into a live backplane without corruption of the data and clock busses. When the connection is made, the LTC4300-1/LTC4300-2 provide bidirectional buffering, keeping the backplane and card capacitances isolated. Rise-time accelerator circuitry* allows the use of weaker DC pull-up currents while still meeting rise-time requirements. During insertion, the SDA and SCL lines are precharged to 1V to minimize bus disturbances. The LTC4300-1 incorporates a CMOS threshold digital ENABLE input pin, which forces the part into a low current mode when driven to ground and sets normal operation when driven to VCC. It also includes an open drain READY output pin, which indicates that the backplane and card sides are connected together. The LTC4300-2 replaces the ENABLE pin with a dedicated supply voltage pin, VCC2, for the card side, providing level shifting between 3.3V and 5V systems. Both the backplane and card may be powered with supply voltages ranging from 2.7V to 5.5V, with no contraints on which supply voltage is higher. The LTC4300-2 also replaces the READY pin with a digital CMOS input pin, ACC, which enables and disables the rise-time accelerator currents. The LTC4300 is available in a small 8-pin MSOP package.
APPLICATIO S
s s s s
Hot Board Insertion Servers Capacitance Buffer/Bus Extender Desktop Computer
, LTC and LT are registered trademarks of Linear Technology Corporation. I2C is a trademark of Philips Electronics N. V. *U.S. Patent No. 6,650,174
TYPICAL APPLICATIO
VCC 3.3V R1 24k SCLIN C2* R2 24k 3 8
Input-Output Connection t PLH
C1 0.01F R3 24k 2 R4 24k SCLOUT C4*
OUTPUT SIDE 50pF INPUT SIDE 150pF
SDAIN C3*
6
7
SDAOUT C5*
1 *CAPACITORS NOT REQUIRED IF BUS IS SUFFICIENTLY LOADED
LTC4300-1 5 READY ENABLE GND 4
4300-1/2 TA01
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LTC4300-1/LTC4300-2
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
VCC to GND .................................................... - 0.5 to 7V VCC2 to GND (LTC4300-2) ............................. - 0.5 to 7V SDAIN, SCLIN, SDAOUT, SCLOUT ................. - 0.5 to 7V READY, ENABLE (LTC4300-1) ....................... - 0.5 to 7V ACC (LTC4300-2) .......................................... - 0.5 to 7V Operating Temperature Range LTC4300-1C/LTC4300-2C ....................... 0C to 70C LTC4300-1I/LTC4300-2I .................... - 40C to 85C Storage Temperature Range ................. - 65C to 125C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER
TOP VIEW ENABLE/VCC2* SCLOUT SCLIN GND 1 2 3 4 8 7 6 5 VCC SDAOUT SDAIN READY/ACC*
LTC4300-1CMS8 LTC4300-1IMS8 LTC4300-2CMS8 LTC4300-2IMS8 MS8 PART MARKING LTUB LTUC LTVJ LTVK
MS8 PACKAGE 8-LEAD PLASTIC MSOP *LTC4300-2
TJMAX = 125C, JA = 200C/W
Consult LTC marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL PARAMETER Power Supply VCC ICC ISD VCC2 IVCC1 IVCC2 Positive Supply Voltage Supply Current Supply Current in Shutdown Mode Card Side Supply Voltage VCC Supply Current VCC2 Supply Current VCC = 5.5V, VSDAIN = VSCLIN = 0V, LTC4300-1 VENABLE = 0V, LTC4300-1 LTC4300-2 VSDAIN = VSCLIN = 0V, VCC1 = VCC2 = 5.5V, LTC4300-2 VSDAOUT = VSCLOUT = 0V, VCC1 = VCC2 = 5.5V, LTC4300-2 SDA, SCL Floating LTC4300-1 LTC4300-1, ENABLE Pin ENABLE from 0V to VCC, LTC4300-1 LTC4300-1 LTC4300-1 LTC4300-1 LTC4300-1 LTC4300-1 IPULLUP = 3mA, LTC4300-1
q q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN 2.7
TYP
MAX 5.5
UNITS V mA A V mA mA
2.8 0.1 2.7 1.8 1.2
6 5.5 3.6 2.4
Start-Up Circuitry VPRE tIDLE VEN VDIS IEN tPHL tPLH IOFF VOL Precharge Voltage Bus Idle Time ENABLE Threshold Voltage Disable Threshold Voltage ENABLE Input Current ENABLE Delay, On-Off READY Delay, Off-On ENABLE Delay, Off-On READY Delay, On-Off READY OFF State Leakage Current READY Output Low Voltage 0.8 50 0.1 * VCC 1.0 95 0.5 * VCC 0.5 * VCC 0.1 100 10 80 10 0.1 0.4 1 1.2 150 0.9 * VCC V s V V A ns ns s s A V
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LTC4300-1/LTC4300-2
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Rise-Time Accelerators IPULLUPAC Transient Boosted Pull-Up Current
The q denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25C. VCC = 2.7V to 5.5V, unless otherwise noted.
CONDITIONS Positive Transition on SDA,SCL, VCC = 2.7V, Slew Rate = 1.25V/s (Note 2), LTC4300-2, ACC = 0.7 * VCC2, VCC2 = 2.7V LTC4300-2 LTC4300-2 LTC4300-2 LTC4300-2 10k to VCC on SDA, SCL, VCC = 3.3V (Note 3), LTC4300-2, VCC2 = 3.3V, VIN = 0.2V Guaranteed by Design, Not Subject to Test Guaranteed by Design, Not Subject to Test SDA, SCL Pins, ISINK = 3mA, VCC = 2.7V, VCC2 = 2.7V, LTC4300-2 SDA, SCL Pins = VCC = 5.5V, LTC4300-2, VCC2 = 5.5V (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Notes 4, 5) (Notes 4, 5) 0 1.3 0.6 0.6 0.6 300 100 1.3 0.6 20 + 0.1 * CB 20 + 0.1 * CB Note 4: Guaranteed by design, not subject to test. Note 5: CB = total capacitance of one bus line in pF. 300 300
q q
MIN 1
TYP 2
MAX
UNITS mA
VACCDIS VACCEN IVACC tPDOFF VOS fSCL, SDA CIN VOL ILEAK
Accelerator Disable Threshold Accelerator Enable Threshold ACC Input Current ACC Delay, On/Off Input-Output Offset Voltage Operating Frequency Digital Input Capacitance Output Low Voltage, Input = 0V Input Leakage Current
0.3 * VCC2
0.5 * VCC2 0.5 * VCC2 0.1 5 0.7 * VCC2 1
V V A ns 150 400 10 0.4 5 mV kHz pF V A
Input-Output Connection 0 0 0 75
Timing Characteristics fI2C tBUF thD,STA tsu,STA tsu,STO thD, DAT tsu, DAT tLOW tHIGH tf tr I2C Operating Frequency Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock, Data Fall Time Clock, Data Rise Time 400 kHz s s s s ns ns s s ns ns
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired Note 2: IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section. Note 3: The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pullup resistor and VCC voltage is shown in the Typical Performance Characteristics section.
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LTC4300-1/LTC4300-2 TYPICAL PERFOR A CE CHARACTERISTICS
ICC vs Temperature (LTC4300-1)
3.0 2.9 2.8
t PHL (ns) ICC (mA)
VCC = 5.5V
2.7 2.6 2.5 2.4 VCC = 2.7V
2.3 2.2 -50 -25 0 25 50 TEMPERATURE (C) 75 100 0 -50
IPULLUPAC vs Temperature
12 10 IPULLUPAC (mA) 8 6 4 2 VCC = 2.7V 0 -50 -25 0 25 50 TEMPERATURE (C) 75 100 0 VCC = 3V VCC = 5V
VOUT - VIN (mV)
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Input - Output tPHL vs Temperature (LTC4300-1)
100 VCC = 2.7V 80 VCC = 3.3V 60
40
VCC = 5.5V
20
CIN = COUT = 100pF RPULLUPIN = RPULLUPOUT = 10k -25 0 25 50 TEMPERATURE (C) 75 100
4300-1/2 G01
4300-1/2 G02
Connection Circuitry VOUT - VIN
300 250 200 150 100 VCC = 5V 50 VCC = 3.3V 0 10,000 20,000 30,000 RPULLUP () 40,000
4300-1/2 G04
TA = 25C VIN = 0V
4300-1/2 G03
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LTC4300-1/LTC4300-2
PI FU CTIO S
ENABLE/VCC2 (Pin 1): Chip Enable Pin/Card Supply Voltage. For the LTC4300-1, this is a digital CMOS threshold input pin. Grounding this pin puts the part in a low current (<1A) mode. It also disables the rise-time accelerators, disables the bus precharge circuitry, drives READY low, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT. Drive ENABLE all the way to VCC for normal operation. Connect ENABLE to VCC if this feature is not being used. For the LTC4300-2, this is the supply voltage for the devices on the card I2C busses. Connect pull-up resistors from SDAOUT and SCLOUT to this pin. Place a bypass capacitor of at least 0.01F close to this pin for best results. SCLOUT (Pin 2): Serial Clock Output. Connect this pin to the SCL bus on the card. See Figures 3 and 4 for bus pullup resistance and capacitance requirements. SCLIN (Pin 3): Serial Clock Input. Connect this pin to the SCL bus on the backplane. See Figures 3 and 4 for bus pullup resistance and capacitance requirements. GND (Pin 4): Ground. Connect this pin to a ground plane for best results. READY/ACC (Pin 5): Connection Flag/Rise-Time Accelerator Control. For the LTC4300-1, this is an open-drain NMOS output which pulls low when either ENABLE is low or the start-up sequence described in the Operation section has not been completed. READY goes high when ENABLE is high and start-up is complete. Connect a 10k resistor from this pin to VCC to provide the pull up. For the LTC4300-2, this is a CMOS threshold digital input pin that enables and disables the rise-time accelerators on all four SDA and SCL pins. Drive ACC all the way to the VCC2 supply voltage to enable all four accelerators; drive ACC to ground to turn them off. SDAIN (Pin 6): Serial Data Input. Connect this pin to the SDA bus on the backplane. See Figures 3 and 4 for bus pull-up resistance and capacitance requirements. SDAOUT (Pin 7): Serial Data Output. Connect this pin to the SDA bus on the card. See Figures 3 and 4 for bus pullup resistance and capacitance requirements. VCC (Pin 8): Main Input Power Supply from Backplane. This is the supply voltage for the devices on the backplane I2C busses. Connect pull-up resistors from SDAIN and SCLIN to this pin. Place a bypass capacitor of at least 0.01F close to this pin for best results.
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LTC4300-1/LTC4300-2
BLOCK DIAGRA
SDAIN 6
SCLIN 3
+ -
STOP BIT AND BUS IDLE 0.5A
+
0.55VCC/ 0.45VCC
-
95s DELAY
UVLO ENABLE 1
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(LTC4300-1) 2-Wire Bus Buffer and Hot SwapTM Controller
2mA SLEW RATE DECTECTOR BACKPLANE-TO-CARD CONNECTION 2mA SLEW RATE DECTECTOR 8 VCC 7 4 SDAOUT
CONNECT CONNECT ENABLE 100k RCH1 1V PRECHARGE 100k RCH2 100k RCH4 100k RCH3
CONNECT
2mA SLEW RATE DECTECTOR BACKPLANE-TO-CARD CONNECTION CONNECT
2mA SLEW RATE DECTECTOR
2 SCLOUT
CONNECT
+ -
0.55VCC/ 0.45VCC
+ -
20pF CONNECT RD QB S
5 READY
4 GND
0.5pF
4300-1 BD
CONNECT
Hot Swap is a trademark of Linear Technology Corporation.
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LTC4300-1/LTC4300-2
BLOCK DIAGRA
VCC 8 2mA SLEW RATE DECTECTOR BACKPLANE-TO-CARD CONNECTION CONNECT 100k RCH1 1V PRECHARGE 100k RCH2 100k RCH4 CONNECT 100k RCH3 CONNECT 2mA SLEW RATE DECTECTOR 1 VCC2
ACC
SDAIN 6
ACC
SCLIN 3
+ -
STOP BIT AND BUS IDLE 0.5A
+
0.55VCC/ 0.45VCC
-
95s DELAY
UVLO
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(LTC4300-2)
2-Wire Bus Buffer and Hot Swap Controller
7 4 SDAOUT
2mA SLEW RATE DECTECTOR BACKPLANE-TO-CARD CONNECTION CONNECT
2mA SLEW RATE DECTECTOR 5 ACC
2 SCLOUT
CONNECT
+ -
0.55VCC2/ 0.45VCC2
+ -
20pF CONNECT CONNECT RD QB S 4 GND 0.5pF
4300-2 BD
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LTC4300-1/LTC4300-2
OPERATIO
Start-Up When the LTC4300 first receives power on its VCC pin, either during power-up or during hot swapping, it starts in an undervoltage lockout (UVLO) state, ignoring any activity on the SDA and SCL pins until VCC rises above 2.5V. For the LTC4300-2, the part also waits for VCC2 to rise above 2V. This ensures that the part does not try to function until it has enough voltage to do so. During this time, the 1V precharge circuitry is also active and forces 1V through 100k nominal resistors to the SDA and SCL pins. Because the I/O card is being plugged into a live backplane, the voltage on the backplane SDA and SCL busses may be anywhere between 0V and VCC. Precharging the SCL and SDA pins to 1V minimizes the worst-case voltage differential these pins will see at the moment of connection, therefore minimizing the amount of disturbance caused by the I/O card. Once the LTC4300 comes out of UVLO, it assumes that SDAIN and SCLIN have been hot swapped into a live system and that SDAOUT and SCLOUT are being powered up at the same time as itself. Therefore, it looks for either a stop bit or bus idle condition on the backplane side to indicate the completion of a data transaction. When either one occurs, the part also verifies that both the SDAOUT and SCLOUT voltages are high. When all of these conditions are met, the input-to-output connection circuitry is activated, joining the SDA and SCL busses on the I/O card with those on the backplane. Connection Circuitry Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low forced on either pin at any time results in both pin voltages being low. SDAIN and SDAOUT enter a logic high state only when all devices on both SDAIN and SDAOUT force a high. The same is true for SCLIN and SCLOUT. This important feature ensures that clock stretching, clock arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to the LTC4300. Another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane and card capacitances isolated. Because of this isolation,
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the waveforms on the backplane busses look slightly different than the corresponding card bus waveforms, as described here. Input to Output Offset Voltage When a logic low voltage, VLOW1, is driven on any of the LTC4300's data or clock pins, the LTC4300 regulates the voltage on the other side of the chip (call it VLOW2) to a slightly higher voltage, as directed by the following equation: VLOW2 = VLOW1 + 50mV + (VCC/R) * 100 where R is the bus pull-up resistance in ohms. For example, if a device is forcing SDAOUT to 10mV and if VCC = 3.3V and the pull-up resistor R on SDAIN is 10k, then the voltage on SDAIN = 10mV + 50mV + (3.3/10000) * 100 = 93mV. See the Typical Performance Characteristics section for curves showing the offset voltage as a function of VCC and R. Propagation Delays During a rising edge, the rise-time on each side is determined by the combined pull-up current of the LTC4300 boost current and the bus resistor and the equivalent capacitance on the line. If the pull-up currents are the same, a difference in rise-time occurs which is directly proportional to the difference in capacitance between the two sides. This effect is displayed in Figure 1 for VCC = 3.3V and a 10k pull-up resistor on each side (50pF on one side and 150pF on the other). Since the output side has less capacitance than the input, it rises faster and the effective tPLH is negative. There is a finite propagation delay, tPHL, through the connection circuitry for falling waveforms. Figure 2 shows the falling edge waveforms for the same VCC, pull-up resistors and equivalent capacitance conditions as used in Figure 1. An external NMOS device pulls down the voltage on the side with 150pF capacitance; the LTC4300 pulls down the voltage on the opposite side, with a delay of 55ns. This delay is always positive and is a function of supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. The Typical Performance Characteristics section shows tPHL
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LTC4300-1/LTC4300-2
OPERATIO
as a function of temperature and voltage for 10k pull-up resistors and 100pF equivalent capacitance on both sides of the part. By comparison with Figure 2, the VCC = 3.3V curve shows that increasing the capacitance from 50pF to 150pF results in a tPHL increase from 55ns to 75ns. Larger output capacitances translate to longer delays (up to 150ns). Users must quantify the difference in propagation times for a rising edge vs a falling edge in their systems and adjust setup and hold times accordingly. Rise-Time Accelerators Once connection has been established, rise-time accelerator circuits on all four SDA and SCL pins are activated. These allow the user to choose weaker DC pull-up currents on the bus, reducing power consumption while still meeting system rise-time requirements. During positive bus transitions, the LTC4300 switches in 2mA of current to quickly slew the SDA and SCL lines once their DC voltages exceed 0.6V. Using a general rule of 20pF of capacitance for every device on the bus (10pF for the device and 10pF for interconnect), choose a pull-up current so that the bus will rise on its own at a rate of at least 1.25V/s to guarantee activation of the accelerators. For example, assume an SMBus system with VCC = 3V, a 10k pull-up resistor and equivalent bus capacitance of 200pF. The rise-time of an SMBus system is calculated from (VIL(MAX) - 0.15V) to (VIH(MIN) + 0.15V), or 0.65V to 2.25V. It takes an RC circuit 0.92 time constants to traverse this voltage for a 3V supply; in this case, 0.92 * (10k * 200pF) = 1.85s. Thus, the system exceeds the maximum allowed rise-time of 1s by 85%. However, using the rise-time accelerators, which are activated at a
OUTPUT SIDE 50pF
Figure 1. Input-Output Connection t PLH
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DC threshold of below 0.65V, the worst-case rise-time is: (2.25V - 0.65V) * 200pF/1mA = 320ns, which meets the 1s rise-time requirement. READY Digital Output (LTC4300-1) This pin provides a digital flag which is low when either ENABLE is low or the start-up sequence described earlier in this section has not been completed. READY goes high when ENABLE is high and start-up is complete. The pin is driven by an open drain pull-down capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor of 10k to VCC to provide the pull-up. This feature is available for the LTC4300-1 only. ENABLE Low Current Disable (LTC4300-1) Grounding the ENABLE pin disconnects the backplane side from the card side, disables the rise-time accelerators, drives READY low, disables the bus precharge circuitry and puts the part in a near-zero current state. When the pin voltage is driven all the way to VCC, the part waits for data transactions on both the backplane and card sides to be complete (as described in the Start-Up section) before reconnecting the two sides. This feature is available for the LTC4300-1 only. ACC Boost Current Enable (LTC4300-2) Users having lightly loaded systems may wish to disable the rise-time accelerators. Driving this pin to ground turns off the rise-time accelerators on all four SDA and SCL pins. Driving this pin to the VCC2 voltage enables normal operation of the rise-time accelerators, as described in the RiseTime Accelerators section above. This feature is available for the LTC4300-2 only.
INPUT SIDE 150pF INPUT SIDE 150pF OUTPUT SIDE 50pF
Figure 2. Input-Output Connection t PHL
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LTC4300-1/LTC4300-2
APPLICATIO S I FOR ATIO
Resistor Pull-Up Value Selection
The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25V/s on the SDA and SCL pins, in order to activate the boost pull-up currents during rising edges. Choose maximum resistor value R using the formula: R (VCC(MIN) - 0.6) (800,000) / C where R is the pull-up resistor value in ohms, VCC(MIN) is the minimum VCC voltage and C is the equivalent bus capacitance in picofarads (pF). In addition, regardless of the bus capacitance, always choose R 16k for VCC = 5.5V maximum, R 24k for VCC = 3.6V maximum. The start-up circuitry requires logic high voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. See the curves in Figures 3 and 4 for guidance in resistor pull-up selection. Minimum SDA and SCL Capacitance Requirements The LTC4300 I/O connection circuitry requires a minimum capacitance loading on the SDA and SCL pins in order to function properly. The value of this capacitance is a function of VCC and the bus pull-up resistance. Estimate the bus capacitance on both the backplane and the card data and clock busses, and refer to Figures 3 and 4 to choose appropriate pull-up resistor values. Note from the
30 25 RMAX = 24k RPULLUP (k)
RPULLUP (k)
20 15 10 RECOMMENDED PULL-UP 5 0
RISE-TIME > 300ns
0
100
200 CBUS (pF)
300
400
4300-1/2 F03
Figure 3. Bus Requirements for 3.3V Systems
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figures that 5V systems must have at least 47pF capacitance on their busses and 3.3V systems must have at least 22pF capacitance for proper operation of the LTC4300. For applications with less capacitance, add a capacitor to ground to ensure these minimum capacitance conditions. Hot Swapping and Capacitance Buffering Application Figures 5 through 8 illustrate the usage of the LTC4300 in applications that take advantage of both its hot swapping and capacitance buffering features. In all of these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise- and fall-time requirements difficult to meet. Placing a LTC4300 on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the LTC4300 drives the capacitance of everything on the card and the backplane must drive only the capacitance of the LTC4300, which is less than 10pF. Figure 5 shows the LTC4300-1 in a CompactPCI TM configuration. Connect V CC to the output of one of the CompactPCI power supply hot swap circuits and connect ENABLE to the short "board enable" pin. VCC is monitored by a filtered UVLO circuit. With the VCC voltage powering up after all other pins have established connection, the UVLO circuit ensures that the backplane and card data and clock busses are not connected until the transients asso20 15 RMAX = 16k RISE-TIME > 300ns 10 RECOMMENDED PULL-UP 5 0 0 100 200 CBUS (pF) 300 400
4300-1/2 F04
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Figure 4. Bus Requirements for 5V Systems
CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.
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LTC4300-1/LTC4300-2
APPLICATIO S I FOR ATIO
ciated with hot swapping have settled. Owing to their small capacitance, the SDAIN and SCLIN pins cause minimal disturbance on the backplane busses when they make contact with the connector. Figure 6 shows the LTC4300-2 in a CompactPCI configuration. The LTC4300-2 receives its VCC voltage from one of the long "early power" pins. Because this power is not switched, add a 5 to 10 resistor between the VCC pins of the connector and the LTC4300-2, as shown in the figure. In addition, make sure that the VCC bypassing on the backplane is large compared to the 0.01F bypass capacitor on the card. Establishing early power VCC ensures that the 1V precharge voltage is present at the SDAIN and SCLIN pins before they make contact. Connect VCC2 to the output of one of the CompactPCI power supply hot swap circuits. VCC2 is monitored by a filtered UVLO circuit. With the VCC2 voltage powering up after all other pins have established connection, the UVLO circuit ensures that the backplane and card data and clock busses are not connected until the transients associated with hot swapping have settled. Figure 7 shows the LTC4300-1 in a PCI application, where all of the pins have the same length. In this case, connect an RC series circuit on the I/O card between VCC and ENABLE. An RC product of 10ms provides a filter to prevent the LTC4300-1 from becoming activated until the transients associated with hot swapping have settled. Figure 8 shows the LTC4300-2 in an application where the user has a custom connector with pins of three different lengths available. Making VCC2 the shortest pin ensures that all other pins are firmly connected before VCC2 receives any voltage. A filtered UVLO circuit on VCC2 ensures that the VCC2 pin is firmly connected before the LTC4300-2 connects the backplane to the card. Repeater/Bus Extender Application Users who wish to connect two 2-wire systems separated by a distance can do so by connecting two LTC4300-1s back-to-back, as shown in Figure 9. The I2C specification allows for 400pF maximum bus capacitance, severely limiting the length of the bus. The SMBus specification
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places no restriction on bus capacitance, but the limited impedances of devices connected to the bus require systems to remain small if rise- and fall-time specifications are to be met. The strong pull-up and pull-down impedances of the LTC4300-1 are capable of meeting riseand fall-time specifications for one nanofarad of capacitance, thus allowing much more interconnect distance. In this situation, the differential ground voltage between the two systems may limit the allowed distance, because a valid logic low voltage with respect to the ground at one end of the system may violate the allowed VOL specification with respect to the ground at the other end. In addition, the connection circuitry offset voltages of the back-to-back LTC4300-1s add together, directly contributing to the same problem. Systems with Disparate Supply Voltages (LTC4300-1) In large 2-wire systems, the VCC voltages seen by devices at various points in the system can differ by a few hundred millivolts or more. This situation is well modelled by a series resistor in the VCC line, as shown in Figure 10. For proper operation of the LTC4300-1, make sure that VCC(BUS) VCC(LTC4300) - 0.5V. 5V to 3.3V Level Translator and Power Supply Redundancy (LTC4300-2) Systems requiring different supply voltages for the backplane side and the card side can use the LTC4300-2, as shown in Figure 11. The pull-up resistors on the card side connect from SDAOUT to SCLOUT to VCC2, and those on the backplane side connect from SDAIN and SCLIN to VCC. The LTC4300-2 functions for voltages ranging from 2.7V to 5.5V on both VCC and VCC2. There is no constraint on the voltage magnitudes of VCC and VCC2 with respect to each other. This application also provides power supply redundancy. If either the VCC or VCC2 voltage falls below its UVLO threshold, the LTC4300-2 disconnects the backplane from the card, so that the side that is still powered can continue to function.
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LTC4300-1/LTC4300-2
APPLICATIO S I FOR ATIO U
POWER SUPPLY HOT SWAP I/O PERIPHERAL CARD 1 C1 0.01F ENABLE SDAIN SCLIN VCC LTC4300-1 U1 GND SDAOUT SCLOUT READY R4 10k R5 10k R6 10k CARD_SDA CARD_SCL POWER SUPPLY HOT SWAP I/O PERIPHERAL CARD 2 C3 0.01F ENABLE SDAIN SCLIN VCC LTC4300-1 U2 GND SDAOUT SCLOUT READY R8 10k R9 10k R10 10k CARD2_SDA CARD2_SCL POWER SUPPLY HOT SWAP I/O PERIPHERAL CARD N C5 0.01F ENABLE SDAIN SCLIN VCC LTC4300-1 U3 GND SDAOUT SCLOUT READY R12 10k R13 10k R14 10k CARDN_SDA CARDN_SCL
BACKPLANE VCC R1 10k BD_SEL SDA SCL R2 10k
BACKPLANE CONNECTOR
STAGGERED CONNECTOR
STAGGERED CONNECTOR
STAGGERED CONNECTOR
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN "PROPER OPERATION" REGION OF FIGURES 3 AND 4
Figure 5. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-1 in a CompactPCI System
12
W
U
U
***
4300-1/2 F05
sn430012 430012fs
LTC4300-1/LTC4300-2
APPLICATIO S I FOR ATIO
BACKPLANE VCC2 BD_SEL VCC SDA SCL R1 10k R2 10k
BACKPLANE CONNECTOR
STAGGERED CONNECTOR
STAGGERED CONNECTOR
STAGGERED CONNECTOR
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN "PROPER OPERATION" REGION OF FIGURES 3 AND 4
Figure 6. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-2 in a CompactPCI System
U
POWER SUPPLY HOT SWAP 5.1 VCC SDAIN SCLIN C2 0.01F I/O PERIPHERAL CARD 1 C1 0.01F VCC2 LTC4300-2 U1 GND SDAOUT SCLOUT ACC R4 10k R5 10k R6 10k CARD_SDA CARD_SCL POWER SUPPLY HOT SWAP 5.1 VCC SDAIN SCLIN C4 0.01F I/O PERIPHERAL CARD 2 C3 0.01F VCC2 LTC4300-2 U2 GND SDAOUT SCLOUT ACC R8 10k R9 10k R10 10k CARD2_SDA CARD2_SCL POWER SUPPLY HOT SWAP 5.1 VCC SDAIN SCLIN C6 0.01F I/O PERIPHERAL CARD N C5 0.01F VCC2 LTC4300-2 U3 GND SDAOUT SCLOUT ACC R12 10k R13 10k R14 10k CARDN_SDA CARDN_SCL
***
4300-1/2 F06
W
U
U
sn430012 430012fs
13
LTC4300-1/LTC4300-2
APPLICATIO S I FOR ATIO
BACKPLANE VCC R1 10k R2 10k BACKPLANE CONNECTOR
SDA SCL C2 0.1F
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN "PROPER OPERATION" REGION OF FIGURES 3 AND 4
Figure 7. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-1 in a PCI System
BACKPLANE CONNECTOR
BACKPLANE VCC2 R1 10k VCC SDA SCL R2 10k
STAGGERED CONNECTOR
STAGGERED CONNECTOR
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN "PROPER OPERATION" REGION OF FIGURES 3 AND 4
Figure 8. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-2 with a Custom Connector
sn430012 430012fs
14
U
I/O PERIPHERAL CARD 1 R3 100k ENABLE SDAIN SCLIN VCC LTC4300-1 U1 GND C1 0.01F SDAOUT SCLOUT READY R4 10k R5 10k R6 10k CARD_SDA CARD_SCL I/O PERIPHERAL CARD 2 R7 100k ENABLE SDAIN SCLIN C4 0.1F VCC LTC4300-1 U2 GND C3 0.01F SDAOUT SCLOUT READY R8 10k R9 10k R10 10k CARD2_SDA CARD2_SCL
4300-1/2 F07
W
U
U
I/O PERIPHERAL CARD 1 C1 0.01F VCC SDAIN SCLIN C2 0.01F VCC2 LTC4300-2 U1 GND SDAOUT SCLOUT ACC R4 10k R5 10k R6 10k CARD_SDA CARD_SCL
I/O PERIPHERAL CARD 2 C3 0.01F VCC SDAIN SCLIN C4 0.01F VCC2 LTC4300-2 U2 GND SDAOUT SCLOUT ACC R8 10k R9 10k R10 10k CARD2_SDA CARD2_SCL
4300-1/2 F08
LTC4300-1/LTC4300-2
APPLICATIO S I FOR ATIO
2-WIRE SYSTEM 1 VCC = 5V
C1 0.01F R1 10k R4 10k R5 10k VCC ENABLE SDA1 SCL1 TO OTHER SYSTEM 1 DEVICES SDAIN SCLIN GND SDAOUT SCLOUT READY LONG DISTANCE BUS SDAOUT SCLOUT READY GND R2 R3 5.1k 5.1k R6 10k
LTC4300-1
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN "PROPER OPERATION" REGION OF FIGURE 4
Figure 9. Repeater/Bus Extender Application
PACKAGE DESCRIPTION
MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 0.127 (.035 .005)
5.23 (.206) MIN
0.42 0.04 (.0165 .0015) TYP
RECOMMENDED SOLDER PAD LAYOUT DETAIL "A" 0 - 6 TYP 4.88 0.1 (.192 .004) 3.00 0.102 (.118 .004) NOTE 4
0.254 (.010) GAUGE PLANE
DETAIL "A" 0.18 (.077) SEATING PLANE
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
sn430012 430012fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
2-WIRE SYSTEM 2 VCC C2 0.01F R7 10k VCC ENABLE SDAIN SCLIN SDA1 SCL1 TO OTHER SYSTEM 2 DEVICES
4300-1/2 F07
U
W
U
U
LTC4300-1
R8 10k
3.2 - 3.45 (.126 - .136)
0.65 (.0256) BSC
3.00 0.102 (.118 .004) (NOTE 3)
8
7 65
0.52 (.206) REF
0.53 0.015 (.021 .006)
1 1.10 (.043) MAX
23
4 0.86 (.034) REF
0.22 - 0.38 (.009 - .015)
0.65 (.0256) BCS
0.13 0.05 (.005 .002)
MSOP (MS8) 1001
15
LTC4300-1/LTC4300-2
TYPICAL APPLICATIO S
RDROP VCC R1 10k R2 10k C2 0.01F ENABLE SDA SCL SDAIN SCLIN VCC LTC4300-1 U1 GND SDAOUT SCLOUT READY VCC_LOW R3 10k R4 10k R5 10k SDA2 SCL2
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN "PROPER OPERATION" REGION OF FIGURES 3 AND 4
VCC 5V R1 10k SCL SCL R4 10k
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN "PROPER OPERATION" REGION OF FIGURES 3 AND 4
RELATED PARTS
PART NUMBER LTC1380/LTC1393 LTC1427-50 LTC1623 LTC1663 LTC1694/LTC1694-1 LT1786F LTC1695 LTC1840 DESCRIPTION Single-Ended 8-Channel/Differential 4-Channel Analog Mux with SMBus Interface Micropower, 10-Bit Current Output DAC with SMBus Interface Dual High Side Switch Controller with SMBus Interface SMBus Interface 10-Bit Rail-to-Rail Micropower DAC SMBus Accelerator SMBus Controlled CCFL Switching Regulator SMBus/I2C Fan Speed Controller in ThinSOTTM Dual I2C Fan Speed Controller COMMENTS Low RON: 35 Single-Ended/70 Differential, Expandable to 32 Single or 16 Differential Channels Precision 50A 2.5% Tolerance Over Temperature, 4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale 8 Selectable Addresses/16-Channel Capability DNL < 0.75LSB Max, 5-Lead SOT-23 Package Improved SMBus/I2C Rise-Time, Ensures Data Integrity with Multiple SMBus/I2C Devices 1.25A, 200kHz, Floating or Grounded Lamp Configurations 0.75 PMOS 180mA Regulator, 6-Bit DAC Two 100A 8-Bit DACs, Two Tach Inputs, Four GPI0
sn430012 430012fs
ThinSOT is a trademark of Linear Technology Corporation.
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
4300-1/2 F08
Figure 10. System with Disparate VCC Voltages
C2 0.01F SDAIN SCLIN VCC VCC2
C1 0.01F SDAOUT SCLOUT ACC
CARD_VCC, 3V R3 10k R2 10k CARD_SDA CARD_SCL
LTC4300-2 U1 GND
4300-1/2 F09
Figure 11. 5V to 3.3V Level Translator
LT/TP 0602 2K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

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